The area that is counted may be more than one polygon -it is the total area of all metal connected to gates without being connected to a source/drain implant. There is one such ratio for each interconnect layer. This leads to the somewhat surprising observation that a very thin gate oxide is less likely to be damaged than a thick gate oxide, because as the oxide grows thinner, the leakage goes up exponentially, but the breakdown voltage shrinks only linearly.Īntenna rules are normally expressed as an allowable ratio of metal area to gate area.
A leaky oxide can prevent a charge from building up to the point of causing oxide breakdown. Leaky gate oxides, although bad for power dissipation, are good for avoiding damage from the antenna effect. In particular, reactive-ion etching of the first metal layer can result in exactly the situation shown - the metal on each net is disconnected from the initial global metal layer, and the plasma etching is still adding charges to each piece of metal. So if a charge is added in any way to the metal 1 shape (as shown by the lightning bolt) it can rise to the level of breaking down the gate oxide. Since metal 2 is not built yet, there is no diode connected to the gate oxide.
This is shown in figure 1(b), which is the situation while metal 1 is being etched. However, during the construction of the chip, the oxide may not be protected by a diode. The source/drain implant forms a diode, which breaks down at a lower voltage than the oxide (either forward diode conduction, or reverse breakdown), and does so non-destructively. Once the chip is fabricated, this cannot happen, since every net has at least some source/drain implant connected to it. Diagram of a MOSFET, showing source/drain implant and gate dielectric. As of 2007, some manufacturers are replacing this oxide with various high-κ dielectric materials which may or may not be oxides, but the effect is still the same.)įigure 2. (Historically, the gate dielectric has been silicon dioxide, so most of the literature refers to gate oxide damage or gate oxide breakdown. This can happen if the net somehow acquires a voltage somewhat higher than the normal operating voltage of the chip. Since the gate dielectric is so thin, only a few molecules thick, a big worry is breakdown of this layer. Each net will include at least one driver, which must contain a source or drain diffusion (in newer technology implantation is used), and at least one receiver, which will consist of a gate electrode over a thin gate dielectric (see Figure 2 for a detailed view of a MOS transistor). Occasionally the phrase antenna effect is used in this context, but this is less common since there are many effects, and the phrase does not make clear which is meant.įigure 1(a) shows a side view of a typical net in an integrated circuit. The word antenna is something of a misnomer in this context-the problem is really the collection of charge, not the normal meaning of antenna, which is a device for converting electromagnetic fields to/from electrical currents. A violation of such rules is called an antenna violation. Factories ( fabs) normally supply antenna rules, which are rules that must be obeyed to avoid this problem. The antenna effect, more formally plasma induced gate oxide damage, is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. M1 and M2 are the first two metal interconnect layers. Figure 1: Illustration of the cause of antenna effect.
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